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| D at a S he et , Rev. 0.6, J un e 2 00 4 HYS64T32000[H/K/L]M-[3.7/5]-A HYS64T64020[H/K/L]M-[3.7/5]-A M e m or y P r o du c t s Pr eli mi na Never stop thinking. DDR2 MDIMM ry Double-Data-Rate-Two SDRAM Micro-DIMM The information in this document is subject to change without notice. Edition 2004-06 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D at a S he et , Rev. 0.6, J un e 2 00 4 HYS64T32000[H/K/L]M-[3.7/5]-A HYS64T64020[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM DDR2 MDIMM M e m or y P r o du c t s Pr eli mi na Never stop thinking. ry HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Preliminary Revision History: Rev. 0.6 Previous Revision: Page All Rev. 0.5 Subjects (major changes since last revision) Added production variants with "H" instead of "L" in product type 2004-06 2004-04 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com Template: mp_a4_v2.3_2004-01-14.fm HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table of Contents 1 1.1 1.2 1.3 2 3 3.1 4 4.1 4.2 5 6 7 8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 8 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ODT (On Die Termination) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Electrical Characteristics & AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Data Sheet 5 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X Preliminary Double-Data-Rate-Two SDRAM Micro-DIMM DDR2 MDIMM HYS64T32000[H/K/L]M-[3.7/5]-A HYS64T64020[H/K/L]M-[3.7/5]-A 1 Overview This chapter gives an overview of the Double-Data-Rate-Two SDRAM Micro-DIMM product family and describes its main characteristics. 1.1 * Features * * * * * * * Burst Refresh, Distributed Refresh and Self Refresh All inputs and outputs SSTL_1.8 compatible OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Serial Presence Detect with E2PROM Micro-DIMM Dimensions (nominal) : 30 mm high, 54.0 mm wide Based on JEDEC standard reference layouts Raw Card "A" & "B" 2-piece type Mezzanine Socket with 0,4 mm contact centers * * * * 214-pin PC2-4200 and PC2-3200 DDR2 SDRAM memory modules for use as main memory when installed in systems such as mobile personal computers. 32M x 64 and 64M x 64 module organisation and 32M x 16 chip organisation JEDEC standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply Built with 512Mb DDR2 SDRAMs in P-TFBGA-84-2 chipsize packages Programmable CAS Latencies (3, 4 and 5), Burst Length (8 & 4) and Burst Type Performance -3.7 Table 1 Product Type Speed Code Speed Grade max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time -5 PC2-3200 3-3-3 200 200 200 15 15 45 60 Units -- MHz MHz MHz ns ns ns ns PC2-4200 4-4-4 fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 266 266 200 15 15 45 60 1.2 Description The memory array is designed with 512Mb DoubleData-Rate-Two (DDR2) Synchronous DRAMs. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer. The INFINEON HYS64T[3200/6402]0[H/K/L]M- [3.7/5]-A module family are low profile Unbuffered Micro-DIMM modules "MDIMMs" with 30,0 mm height based on DDR2 technology. DIMMs are available as 32M x 64 and 64M x 64 organisation and density, intended for mounting into 214-pin mezzanine connector sockets. Data Sheet 6 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 2 Ordering Information Compliance Code Description SDRAM Technology Overview Product Type HYS64T64020KM-3.7-A HYS64T32000KM-3.7-A HYS64T64020KM-5-A HYS64T32000KM-5-A HYS64T64020HM-3.7-A HYS64T64020LM-3.7-A HYS64T32000HM-3.7-A HYS64T32000LM-3.7-A HYS64T64020HM-5-A HYS64T64020LM-5-A HYS64T32000HM-5-A HYS64T32000LM-5-A 512MB 2Rx16 PC2-4200M-444-11-A0 two ranks 512 MByte DIMM 512 Mbit (x16) 256MB 1Rx16 PC2-4200M-444-11-B0 one rank 256 MByte DIMM 512MB 2Rx16 PC2-3200M-333-11-A0 two ranks 512 MByte DIMM 256MB 1Rx16 PC2-3200M-333-11-B0 one rank 256 MByte DIMM 512MB 2Rx16 PC2-4200M-444-11-A0 two ranks 512 MByte DIMM 512 Mbit (x16) 512MB 2Rx16 PC2-4200M-444-11-A0 two ranks 512 MByte DIMM 256MB 1Rx16 PC2-4200M-444-11-B0 one rank 256 MByte DIMM 256MB 1Rx16 PC2-4200M-444-11-B0 one rank 256 MByte DIMM 512MB 2Rx16 PC2-3200M-333-11-A0 two ranks 512 MByte DIMM 512MB 2Rx16 PC2-3200M-333-11-A0 two ranks 512 MByte DIMM 256MB 1Rx16 PC2-3200M-333-11-B0 one rank 256 MByte DIMM 256MB 1Rx16 PC2-3200M-333-11-B0 one rank 256 MByte DIMM All product types end with a place code, designating the silicon die revision. Example: HYS72T64000KM-5-A, indicating Rev. A dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see Chapter 8 of this data sheet. The Compliance Code is printed on the module label and provides technical details to the user, e. g. "512MB 2Rx16 PC2-4200M-444-11-A0" where "512MB" tells the density in megabytes, "2R x16" means 2 ranks on module built of x16 components, "PC2-4200M" means DDR2 Micro-DIMM with 4.26 GB/s module bandwidth, "444-11" means CAS latency of 4, RCD1) latency of 4, and RP2) latency of 4 using JEDEC SPD revision 1.1, and "A0" means JEDEC raw card A revision 0. Table 3 DIMM Density 256 MByte 512 MByte Table 4 Address Format Module Organization 32M x 64 64M x 64 Memory Ranks 1 2 # of SDRAMs 4 8 # of row/bank/column bits 13/2/10 13/2/10 Raw Card B A Components on Modules1) DRAM Components 2) Product Type HYS64T32000HM HYS64T32000LM2) HYS64T32000KM HYS64T64020HM HYS64T64020LM2) HYS64T64020KM 2) Green Product 2) DRAM Density 512 Mbit 512 Mbit 512 Mbit 512 Mbit DRAM Organisation 32M x 16 32M x 16 32M x 16 32M x 16 HYB18T512160AF 2) HYB18T512160AC HYB18T512160AF 2) HYB18T512160AC 1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. 1) RCD: Row Column Delay 2) RP: Row Precharge Data Sheet 7 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary 1.3 Pin Configuration Overview The pin configuration of the DDR2 SDRAM Micro-DIMM is listed by function in Table 5 (214 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1. Table 5 Pin# Clock Signals 122 194 123 195 43 147 Control Signals 165 62 S0 S1 NC 163 60 56 Address Signals 55 162 161 159 52 158 51 50 157 48 155 154 54 47 153 BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 I I I I I I I I I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Input 11 Address Input 12 Address Input 10/Autoprecharge Address Inputs 9:0 Bank Address 1:0 RAS CAS WE I I NC I I I SSTL SSTL SSTL SSTL SSTL Chip Select Rank 0 Chip Select Rank 1 Note: 2-rank module Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable CK0 CK1 CK0 CK1 CKE0 CKE1 NC I I I I I I NC SSTL SSTL SSTL SSTL SSTL SSTL Clock Enables Note: 2-rank module Note: 1-rank module Complement Clock Signals 1:0 Clock Signals 1:0 Pin Configuration of MDIMM Name Pin Type Buffer Type Function Data Sheet 8 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 5 Pin# Data Signals 3 4 9 10 109 110 114 115 12 13 21 22 117 118 125 126 24 25 30 31 128 129 133 134 33 34 38 39 136 137 142 143 67 68 73 74 174 175 179 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 63:0 Pin Configuration of MDIMM Name Pin Type Buffer Type Function Overview Data Sheet 9 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 5 Pin# 180 76 77 81 82 182 183 188 189 84 85 92 93 191 192 200 201 95 96 101 102 203 204 208 209 112 120 131 36 177 79 90 206 Pin Configuration of MDIMM Name DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Masks 7:0 Note: See block diagram for corresponding DQ M signals Function Data Bus 63:0 Overview Data Sheet 10 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 5 Pin# 7 6 19 18 28 27 140 139 71 70 186 185 198 197 99 98 EEPROM 105 104 211 213 Power Supplies 1 SCL SDA SA0 SA1 I I/O I I AI PWR PWR GND CMOS OD CMOS CMOS - - - - I/O Reference Voltage Power Supply EEPROM Power Supply Ground Plane Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address 1:0 Pin Configuration of MDIMM Name DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function Data Strobes 7:0 Note: See block diagram for corresponding DQS signals Overview VREF 42, 45, 49, 53, 57, 61, 64, 146, 149, VDD 152, 156, 160, 164, 168, 171 VDDSPD 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, VSS 107 35, 37, 40, 66, 69, 72, 75, 78, 80, 83, 86, 89, 91, 94, 97, 100, 103, 108, 111, 113, 116, 119, 121, 124, 127, 130, 132, 135, 138, 141, 144, 173, 176, 178, 181, 184, 187, 190, 193, 196, 205, 199, 202, 207, 210 Other Pins 166 63 ODT0 ODT1 NC 15, 16, 41, 44, 46, 58, 59, 65, 87, 88, NC 106, 145, 148, 150, 151, 167, 169, 170, 172, 212, 214 On-Die Termination Control 1:0 Note: 2-rank module Note: 1-rank module NC - Not connected Note: Pins not MDIMMs connected on Infineon Data Sheet 11 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 6 Abbreviation I O I/O AI PWR GND NC Abbreviations for Pin Type Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected Overview Table 7 Abbreviation SSTL Abbreviations for Buffer Type Description Serial Stub Terminated Logic (SSTL_1.8) CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. CMOS OD Data Sheet 12 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Overview V REF - Pin 001 DQ0 - Pin 003 V SS - Pin 005 DQS0 - Pin 007 DQ2 - Pin 009 V SS - Pin 011 DQ9 - Pin 013 NC - Pin 015 V SS - Pin 017 DQS1 - Pin 019 DQ10 - Pin 021 V SS - Pin 023 DQ17 - Pin 025 DQS2 - Pin 027 V SS - Pin 029 DQ19 - Pin 031 DQ24 - Pin 033 V SS - Pin 035 V SS - Pin 037 DQ27 - Pin 039 NC - Pin 041 CKE0 - Pin 043 V DD - Pin 045 A11 - Pin 047 V DD - Pin 049 A4 - Pin 051 V DD - Pin 053 BA0 - Pin 055 V DD - Pin 057 NC - Pin 059 V DD - Pin 061 ODT1 - Pin 063 NC - Pin 065 DQ32 - Pin 067 V SS - Pin 069 DQS4 - Pin 071 DQ34 - Pin 073 V SS - Pin 075 DQ41 - Pin 077 DM5 - Pin 079 DQ42 - Pin 081 V SS - Pin 083 DQ49 - Pin 085 NC - Pin 087 V SS - Pin 089 V SS - Pin 091 DQ51 - Pin 093 DQ56 - Pin 095 V SS - Pin 097 DQS7 - Pin 099 DQ58 - Pin 101 V SS - Pin 103 SCL - Pin 105 V DDSPD - Pin 107 V SS - Pin 002 DQ1 - Pin 004 DQS0 - Pin 006 V SS - Pin 008 DQ3 - Pin 010 DQ8 - Pin 012 V SS - Pin 014 NC - Pin 016 DQS1 - Pin 018 V SS - Pin 020 DQ11 - Pin 022 DQ16 - Pin 024 V SS - Pin 026 DQS2 - Pin 028 DQ18 - Pin 030 V SS - Pin 032 DQ25 - Pin 034 DM3 - Pin 036 DQ26 - Pin 038 V SS - Pin 040 V DD - Pin 042 NC - Pin 044 NC/BA2 - Pin 046 A7 - Pin 048 A5 - Pin 050 A2 - Pin 052 A10/AP - Pin 054 WE - Pin 056 NC - Pin 058 CAS - Pin 060 S1 V DD V SS DQ33 Pin 062 Pin 064 Pin 066 Pin 068 Pin 109 - DQ4 Pin 111 - V SS Pin 113 - V SS Pin 115 - DQ7 Pin 117 - DQ12 Pin 119 - V SS Pin 121 - V SS Pin 123 - CK0 Pin 125 - DQ14 Pin 127 - V SS Pin 129 - DQ21 Pin 131 - DM2 Pin 133 - DQ22 Pin 135 - V SS Pin 137 - DQ29 Pin 139 - DQS3 Pin 141 - V SS Pin 143 - DQ31 Pin 145 - NC Pin 147 - CKE1 Pin 149 - V DD Pin 151 - NC Pin 153 - A12 Pin 155 - A8 Pin 157 - A6 Pin 159 - A1 Pin 161 - A0 Pin 163 - RAS Pin 165 - S0 Pin 167 - NC Pin 169 - NC Pin 171 - V DD Pin 173 - V SS Pin 175 - DQ37 Pin 177 - DM4 Pin 179 - DQ38 Pin 181 - V SS Pin 183 - DQ45 Pin 185 - DQS5 Pin 187 - V SS Pin 189 - DQ47 Pin 191 - DQ52 Pin 193 - V SS Pin 195 - CK1 Pin 197 - DQS6 Pin 199 - V SS Pin 201 - DQS5 Pin 203 - DQ60 Pin 205 - V SS Pin 207 - V SS Pin 209 - DQ63 Pin 211 - SA0 Pin 213 - SA1 Pin 108 - V SS Pin 110 - DQ5 Pin 112 - DM0 Pin 114 - DQ6 Pin 116 - V SS Pin 118 - DQ13 Pin 120 - DM1 Pin 122 - CK0 Pin 124 - V SS Pin 126 - DQ15 Pin 128 - DQ20 Pin 130 - V SS Pin 132 - V SS Pin 134 - DQ23 Pin 136 - DQ28 Pin 138 - V SS Pin 140 - DQS3 Pin 142 - DQ30 Pin 144 - V SS Pin 146 - V DD Pin 148 - NC Pin 150 - NC Pin 152 - V DD Pin 154 - A9 Pin 156 - V DD Pin 158 - A3 Pin 160 - V DD Pin 162 - BA1 Pin 164 - V DD Pin 166 - ODT0 Pin 168 - V DD Pin 170 - NC Pin 172 - NC Pin 174 - DQ36 Pin 176 - V SS Pin 178 - V SS Pin 180 - DQ39 Pin 182 - DQ44 Pin 184 - V SS Pin 186 - DQS5 Pin 188 - DQ46 Pin 190 - V SS Pin 192 - DQ53 Pin 194 - CK1 Pin 196 - V SS Pin 198 - DQS6 Pin 200 - DQ54 Pin 202 - V SS Pin 204 - DQ61 Pin 206 - DM7 Pin 208 - DQ62 Pin 210 - V SS Pin 212 - NC Pin 214 - NC DQS4 - Pin 070 V SS - Pin 072 DQ35 - Pin 074 DQ40 - Pin 076 V SS - Pin 078 V SS - Pin 080 DQ43 - Pin 082 DQ48 - Pin 084 V SS - Pin 086 NC - Pin 088 DM6 - Pin 090 DQ50 - Pin 092 V SS - Pin 094 DQ57 - Pin 096 DQS7 - Pin 098 V SS - Pin 100 DQ59 - Pin 102 SDA - Pin 104 NC - Pin 106 Figure 1 Pin Configuration for Two-Piece Mezzanine Socket on MDIMM (214 pins) Data Sheet 13 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 8 Symbol CK[1:0], CK[1:0] Input/Output Functional Description Type I Polarity Function Cross point The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down Mode or the Self Refresh Mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. When sampled at the cross point of the rising edge of CK,and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM. Selects internal SDRAM memory bank Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM mode register. During a Bank Activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA[1:0] inputs. If AP is low, then BA[1:0] are used to define which bank to precharge. Data Input/Output pins The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sourced by the DDR2 SDRAM and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS through a 20 to 10 k resistor and DDR2 SDRAM mode registers programmed appropriately. Power supplies for core, I/O, Serial Presence Detect, and ground for the module. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected from SDA to to VDDSPD on the motherboard to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. Address pins used to select the Serial Presence Detect base address. Overview CKE[1:0] I Active High Active Low S[1:0] I RAS, CAS, I WE BA[1:0] ODT[1:0] A[9:0], A10/AP, A[12:11] I I I Active Low -- Active High -- DQ[63:0] DM[7:0] I/O I -- Active High Cross point DQS[7:0], DQS[7:0] I/O VDD, Supply -- VDDSPD, VSS SDA I/O -- SCL SA[1:0] I I -- -- Data Sheet 14 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Block Diagrams 2 BA0 - BA1 A0 - An RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0 CK0 CK1 CK1 S0 S1 DM0 DQS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1 DQS1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM2 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM3 DQS3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Block Diagrams BA0 - BA1: SDRAMs D0 - D7 A0 - An: SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 WE: SDRAMs D0 - D7 CKE0: SDRAMs D0 - D3 CKE1: SDRAMs D4 - D7 ODT0: SDRAMs D0 - D3 ODT1: SDRAMs D4 - D7 4 loads 4 loads VDD,SPD VDD/VDDQ VREF VSS VDD: SPD EEPROM E0 VDD/V DDQ: SDRAMs D0 - D7 VREF: SDRAMs D0 - D7 VSS: SDRAMs D0 - D7 E0 SCL SCL SDA SDA SA0 A0 SA1 A1 A2 WP Vss CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CS D0 CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CS D4 DM4 DQS4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM5 DQS5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D5 DM6 DQS6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM7 DQS7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CS D2 CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CS D6 D1 D3 D7 MPBT0010 Figure 2 Notes Block Diagram Raw Card A (x64, 2 Ranks, x16) 2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1, CKEO, CKE1 resistors are 3 5 % 15 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X 1. DQ, DQS, DM resistors are 22 5 % Data Sheet HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Block Diagrams BA0 - BA1 A0 - An RAS CAS WE VSS CKE0 ODT0 S0 CK0 CK0 CK1 CK1 SCL SDA SA0 SA1 2 loads 2 loads SCL SDA A0 A1 A2 WP BA0 - BA1: SDRAMs D0 - D3 A0 - An: SDRAMs D0 - D3 RAS: SDRAMs D0 - D3 CAS: SDRAMs D0 - D3 WE: SDRAMs D0 - D3 VSS: SDRAMs D0 - D3 CKE: SDRAMs D0 - D3 ODT: SDRAMs D0 - D3 VDD,SPD VDD/VDDQ VREF VSS VDD: SPD EEPROM E0 VDD/V DDQ: SDRAMs D0 - D3 VREF: SDRAMs D0 - D3 VSS: SDRAMs D0 - D3 E0 Vss DM0 DQS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1 DQS1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM2 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM3 DQS3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDM CS LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 LDM CS LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 D0 D1 DM4 DQS4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM5 DQS5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM6 DQS6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM7 DQS7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDM CS LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 LDM CS LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 D2 D3 MPBT0020 Figure 3 Notes Block Diagram Raw Card B (x64, 1 Rank, x16) 3. Load matching Capacitors on BA0 - BA1, A0 - An, RAS, CAS, WE, with 8 pF 0.5pF 1. DQ, DQS, DM resistors are 22 5 % 2. S0, BAn, An, RAS, CAS, WE, ODTO, CKEO resistors are 3 5 % Data Sheet 16 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Electrical Characteristics 3 3.1 Table 9 Parameter Electrical Characteristics Operating Conditions Absolute Maximum Ratings Symbol Values Min. Max. 2.3 2.3 2.3 95 V V V % - 0.5 - 1.0 - 0.5 5 Unit Note/Test Condition 1) 1) 1) 1) VIN, VOUT Voltage on VDD relative to VSS VDD Voltage on VDDQ relative to VSS VDDQ Storage Humidity (without condensation) HSTG Voltage on any pins relative to VSS 1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Table 10 Parameter Operating Conditions Symbol Values min. max. +65 +95 +100 69 90 C C C kPa % 5) 1)2)3)4) Unit Notes Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative) TOPR TCASE TSTG HOPR 0 0 - 50 105 10 1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For measurement conditions, please refer to the JEDEC document JESD51-2 2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported 3) Above 85 C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s 4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 C Case Temperature before initiating Self-Refresh operation. 5) Up to 3000 m. Table 11 Parameter Supply Voltage Levels and DC Operating Conditions Symbol VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) Limit Values min. nom. 1.8 1.8 0.5 x VDDQ -- -- -- max. 1.9 1.9 0.51 x VDDQ 3.6 VDDQ + 0.3 VREF - 0.125 V V V V V V -- 1) 2) Unit Notes Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low 1.7 1.7 0.49 x VDDQ 1.7 VREF + 0.125 - 0.30 1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise in VDDQ. Data Sheet 17 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary IDD Specifications and Conditions 4 Table 12 Parameter IDD Specifications and Conditions IDD Measurement Conditions1)2) Symbol Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. IDD1 IDD2P IDD2N Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Power-Down Current All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "0" (Fast Power-down Exit); Active Power-Down Current All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "1" (Slow Power-down Exit); Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B Distributed Refresh Current IDD5D tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Data Sheet 18 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 12 Parameter IDD Specifications and Conditions IDD Measurement Conditions1)2) (cont'd) Symbol IDD6 Self-Refresh Current CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 C max. All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA. 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) For details and notes see the relevant INFINEON component data sheet Table 13 IDD Specification HYS64T32000HM-3.7-A HYS64T32000LM-3.7-A HYS64T32000KM-3.7-A HYS64T64020HM-3.7-A HYS64T64020LM-3.7-A HYS64T64020KM-3.7-A Unit Notes HYS64T32000HM-5-A HYS64T32000LM-5-A HYS64T32000KM-5-A HYS64T64020HM-5-A HYS64T64020LM-5-A HYS64T64020KM-5-A 512 MB 2 Ranks x64 Max. 296 316 32 256 200 104 40 280 356 376 496 40 32 856 Product Type Organization 256 MB 1 Rank x64 256 MB 1 Rank x64 Max. 320 360 16 160 120 64 20 160 400 440 520 24 16 880 512 MB 2 Ranks x64 Max. 336 376 32 320 240 128 40 320 416 456 536 40 32 896 mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1)2) 1)2) 1)3) 1)3) 1)3) 1)3) 1)3) 1)3) 1)2) 1)2) 1)2) 1)3) 1)3) 1)2) Symbol Max. 280 300 16 128 100 52 20 140 340 360 480 24 16 840 IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. 2) For 2-rank modules only: The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) For 2-rank modules only: Both ranks are in the same IDD mode Data Sheet 19 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary 4.1 IDD Test Conditions IDD Specifications and Conditions For testing the IDD parameters, the timing parameters as in Table 14 are used. Table 14 Parameter IDD Measurement Test Condition Symbol -3.7 -5 Unit PC2-4200-4-4-4 PC2-3200-3-3-3 CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval CLmin 4 3.75 15 60 10 45 15 105 7.8 3 5 15 60 10 45 15 105 7.8 tCK ns ns ns ns ns ns ns s tCKmin tRCDmin tRCmin tRRDmin tRASmin tRPmin tRFCmin tREFI 4.2 ODT (On Die Termination) Current current consumption for any terminated input pin, depends on the input pin is in tri-state or driving "0" or "1", as long a ODT is enabled during a given period of time. The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A[6,2] in the EMRS(1) a "weak" or "strong" termination can be selected. The Table 15 Parameter ODT current per terminated pin Symbol min. 5 2.5 10 5 typ. 6 3 12 6 max. Unit 7.5 3.75 15 7.5 EMRS(1) State Enabled ODT current per DQ IODTO ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING. mA/DQ A6 = 0, A2 = 1 mA/DQ A6 = 1, A2 = 0 mA/DQ A6 = 0, A2 = 1 mA/DQ A6 = 1, A2 = 0 IODTT Note: For power consumption calculations the ODT duty cycle has to be taken into account Data Sheet 20 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Electrical Characteristics & AC Timings 5 Table 16 Parameter Electrical Characteristics & AC Timings AC Timing - Absolute Specifications -5/-3.71) Symbol -3.7 PC2-4200M Min. Max. +500 -- 0.55 8000 8000 -- 0.55 -- -5 PC2-3200M Min. -600 2 0.45 5000 5000 3 0.45 WR + tRP Max. +600 -- 0.55 8000 8000 -- 0.55 -- ps Unit Notes DQ output access time from CK/CK CAS A to CAS B Command Period CK, CK high-level width Clock cycle time CKE minimum high and low pulse width CK, CK low-level width Auto precharge write recovery + precharge time tAC tCCD tCH tCK3 tCK4 tCKE tCL tDAL -500 2 0.45 5000 3750 3 0.45 WR + tRP tCK tCK ps ps 2) 3) tCK tCK tCK ns ps Minimum time clocks remain ON tDELAY after CKE asynchronously drops low DQ and DM input hold time DQ and DM input pulse width (each input) DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (write cycle) DQS falling edge to CLK setup time (write cycle) Clock Half Period Data-out high-impedance time from CK/CK Address and control input hold time Control and Addr. input pulse width (each input) DQ low-impedance from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data Sheet tIS + tCK + tIH -- 225 0.35 -450 0.35 -- WL - 0.25 100 0.2 0.2 min. (tCL, tCH) -- 375 0.6 250 2xtACmin -- -- +450 -- 300 tIS + tCK+ tIH -- 275 0.35 -500 0.35 -- -- -- +500 -- 350 tDH tDIPW tCK ps DQS output access time from CK/CK tDQSCK tDQSL,H tDQSQ tDQSS tCK ps WL + 0.25 WL - 0.25 -- -- -- 150 0.2 0.2 min. (tCL, tCH) WL + 0.25 tCK -- -- -- ps tDS DQS falling edge hold time from CLK tDSH tDSS tHP tHZ tIH tIPW tCK tCK tCK tACmax -- -- -- -- 475 0.6 350 2xtACmin tACmax -- -- -- ps ps tCK ps ps ps Address and control input setup time tIS tLZ(DQ) tLZ(DQS) tMRD tOIT tACmin 2 0 21 tACmax tACmax -- 12 tACmin 2 0 tACmax tACmax -- 12 tCK ns Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 16 Parameter AC Timing - Absolute Specifications -5/-3.71) Symbol -3.7 PC2-4200M Min. Data Output hold time from DQS Data hold skew factor Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay (with and without Auto-Precharge) delay Average Periodic Refresh Interval Auto-refresh to Active/Auto-refresh command period Precharge command period Read preamble Read postamble Active bank A to Active bank B command Max. -- 400 70000 -- -- 7.8 3.9 -- -- 1.1 0.60 -- -- -- 0.60 -- -- -- -5 PC2-3200M Min. Max. -- 450 70000 -- -- 7.8 3.9 -- -- 1.1 0.60 -- -- -- 0.60 -- -- -- Unit Notes Electrical Characteristics & AC Timings tQH tQHS tRAS tRC tRCD tREFI tRFC tRP tRPRE tRPST tRRD tHP-tQHS -- 45 60 15 -- -- 105 15 0.9 0.40 10 7.5 0.25 0.40 15 7.5 2 tHP-tQHS -- 45 60 15 -- -- 105 15 0.9 0.40 10 7.5 0.25 0.40 15 10 2 tCK ps ns ns ns s s ns ns 4) 5) tCK tCK ns ns Internal read to precharge command tRTP delay tWPRE Write postamble tWPST Write recovery time tWR Internal write to read command delay tWTR Exit power down to any valid tXARD Write preamble command (other than NOP or Deselect) Exit active power-down mode to read tXARDS command (slew exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-read command Exit Self-Refresh to read command 2) CL = 3 3) CL = 4 & 5 4) 0 C TCASE 85 C 5) 85 C < TCASE 95 C tCK tCK ns ns tCK 6 - AL 2 -- -- 6 - AL 2 -- -- tCK tCK tXP tXSNR tXSRD tRFC + 10 200 -- -- tRFC + 10 200 -- -- ns tCK 1) For details and notes see the relevant INFINEON component datasheet Data Sheet 22 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 17 Symbol Electrical Characteristics & AC Timings ODT AC Electrical Characteristics and Operating Conditions (all speed bins) Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off Modes) Min. 2 Max. 2 Unit tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tCK ns ns tAC(min) tAC(min) + 2 ns 2.5 tAC(max) + 1 ns 2 tCK + tAC(max) + 1 ns 2.5 tCK ns ns tAC(min) ODT turn-off delay (Power-Down tAC(min) + 2 ns ODT to Power Down Mode Entry 3 Latency ODT Power Down Exit Latency 8 tAC(max) + 0.6 ns 2.5 tCK + tAC(max) + 1 ns -- -- tCK tCK Data Sheet 23 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary SPD Codes 6 Table 18 SPD Codes SPD Codes for PC2-4200M and PC2-3200M HYS64T64020KM-3.7-A HYS64T64020HM-3.7-A HYS64T32000KM-3.7-A HYS64T32000HM-3.7-A HYS64T64020LM-3.7-A HYS64T32000LM-3.7-A HYS64T64020KM-5-A HYS64T64020HM-5-A HYS64T32000KM-5-A 80 08 08 0D 0A 60 40 00 05 50 60 00 82 10 00 00 0C 04 38 00 08 00 HYS64T32000HM-5-A 80 08 08 0D 0A 60 40 00 05 50 60 00 82 10 00 00 0C 04 38 00 08 00 HYS64T64020LM-5-A HYS64T32000LM-5-A x64 1 Rank (x16) Rev 1.1 80 08 08 0D 0A 61 40 00 05 50 60 00 82 10 00 00 0C 04 38 00 08 00 80 08 08 0D 0A 60 40 00 05 50 60 00 82 10 00 00 0C 04 38 00 08 00 Product Type Organization 512 MByte x64 2 Ranks (x16) 256 MByte x64 1 Rank (x16) Rev 1.1 80 08 08 0D 0A 61 40 00 05 3D 50 00 82 10 00 00 0C 04 38 00 08 00 80 08 08 0D 0A 60 40 00 05 3D 50 00 82 10 00 00 0C 04 38 00 08 00 80 08 08 0D 0A 60 40 00 05 3D 50 00 82 10 00 00 0C 04 38 00 08 00 80 08 08 0D 0A 60 40 00 05 3D 50 00 82 10 00 00 0C 04 38 00 08 00 512 MB x64 2 Ranks (x16) Rev 1.1 80 08 08 0D 0A 61 40 00 05 50 60 00 82 10 00 00 0C 04 38 00 08 00 80 08 08 0D 0A 61 40 00 05 50 60 00 82 10 00 00 0C 04 38 00 08 00 256 MB Label Code Jedec SPD Revision Byte# Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of DIMM Ranks Data Width not used Interface Voltage Levels PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333 Rev 1.1 80 08 08 0D 61 40 00 05 3D 50 80 08 08 0D 0A 61 40 00 05 3D 50 00 82 10 00 00 0C 04 38 00 08 00 HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX Number of Column Addresses 0A tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support (non- 00 / ECC) Refresh Rate/Type Primary SDRAM Width not used Burst Length Supported Number of Banks on SDRAM Device CAS Latency not used DIMM Type Information DIMM Attributes 82 10 00 0C 04 38 00 08 00 Error Checking SDRAM Width 00 Data Sheet 24 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 18 SPD Codes for PC2-4200M and PC2-3200M HYS64T64020KM-3.7-A HYS64T64020HM-3.7-A HYS64T32000KM-3.7-A HYS64T32000HM-3.7-A HYS64T64020LM-3.7-A HYS64T32000LM-3.7-A HYS64T64020KM-5-A HYS64T64020HM-5-A HYS64T32000KM-5-A 01 50 60 50 60 3C 28 3C 2D 40 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 72 42 HYS64T32000HM-5-A 01 50 60 50 60 3C 28 3C 2D 40 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 72 42 HYS64T64020LM-5-A HYS64T32000LM-5-A x64 1 Rank (x16) Rev 1.1 01 50 60 50 60 3C 28 3C 2D 40 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 72 42 01 50 60 50 60 3C 28 3C 2D 40 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 72 42 SPD Codes Product Type Organization 512 MByte x64 2 Ranks (x16) 256 MByte x64 1 Rank (x16) Rev 1.1 01 3D 50 50 60 3C 28 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 01 3D 50 50 60 3C 28 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 01 3D 50 50 60 3C 28 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 01 3D 50 50 60 3C 28 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 512 MB x64 2 Ranks (x16) Rev 1.1 01 50 60 50 60 3C 28 3C 2D 40 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 72 42 01 50 60 50 60 3C 28 3C 2D 40 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 00 51 72 42 256 MB Label Code Jedec SPD Revision Byte# Description 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Component Attributes PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333 Rev 1.1 01 3D 50 50 60 3C 28 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 72 52 01 3D 50 50 60 3C 28 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tCK @ CLmax -2 (Byte 18) [ns] tAC SDRAM @ CLmax -2 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns] tWR [ns] tWTR [ns] tRTP [ns] Analysis Characteristics tRC and tRFC extension tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] PLL Relock Time Psi(T-A) DRAM DT0 Tc(max) Delta / DT4R4W Delta 53 Data Sheet 25 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 18 SPD Codes for PC2-4200M and PC2-3200M HYS64T64020KM-3.7-A HYS64T64020HM-3.7-A HYS64T32000KM-3.7-A HYS64T32000HM-3.7-A HYS64T64020LM-3.7-A HYS64T32000LM-3.7-A HYS64T64020KM-5-A HYS64T64020HM-5-A HYS64T32000KM-5-A 23 1D 19 1C 16 2E 1A 2D 00 00 00 00 11 11 C1 00 00 00 00 00 00 00 xx 36 34 54 33 HYS64T32000HM-5-A 23 1D 19 1C 16 2E 1A 2D 00 00 00 00 11 11 C1 00 00 00 00 00 00 00 xx 36 34 54 33 HYS64T64020LM-5-A HYS64T32000LM-5-A x64 1 Rank (x16) Rev 1.1 23 1D 19 1C 16 2E 1A 2D 00 00 00 00 11 12 C1 00 00 00 00 00 00 00 xx 36 34 54 36 23 1D 19 1C 16 2E 1A 2D 00 00 00 00 11 11 C1 00 00 00 00 00 00 00 xx 36 34 54 33 SPD Codes Product Type Organization 512 MByte x64 2 Ranks (x16) 256 MByte x64 1 Rank (x16) Rev 1.1 2B 1D 1D 23 16 36 1C 30 00 00 00 00 11 C0 C1 00 00 00 00 00 00 00 xx 36 34 54 36 2B 1D 1D 23 16 36 1C 30 00 00 00 00 11 BF C1 00 00 00 00 00 00 00 xx 36 34 54 33 2B 1D 1D 23 16 36 1C 30 00 00 00 00 11 BF C1 00 00 00 00 00 00 00 xx 36 34 54 33 2B 1D 1D 23 16 36 1C 30 00 00 00 00 11 BF C1 00 00 00 00 00 00 00 xx 36 34 54 33 512 MB x64 2 Ranks (x16) Rev 1.1 23 1D 19 1C 16 2E 1A 2D 00 00 00 00 11 12 C1 00 00 00 00 00 00 00 xx 36 34 54 36 23 1D 19 1C 16 2E 1A 2D 00 00 00 00 11 12 C1 00 00 00 00 00 00 00 xx 36 34 54 36 256 MB Label Code Jedec SPD Revision Byte# Description 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 DT2N (UDIMM) or DT2Q (RDIMM) DT2P DT3N DT3Pfast DT3Pslow DT4R / DT4R4W Sign DT5B DT7 Psi(ca) PLL Psi(ca) REG DTPLL DTREG / Toggle Rate SPD Revision Checksum of Byte 0-62 PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333 Rev 1.1 2B 1D 1D 23 16 36 1C 30 00 00 00 00 11 C0 2B 1D 1D 23 16 36 1C 30 00 00 00 00 11 C0 C1 00 00 00 00 00 00 00 xx 36 34 54 36 HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX JEDEC ID Code of Infineon (1) C1 JEDEC ID Code of Infineon (2) 00 JEDEC ID Code of Infineon (3) 00 JEDEC ID Code of Infineon (4) 00 JEDEC ID Code of Infineon (5) 00 JEDEC ID Code of Infineon (6) 00 JEDEC ID Code of Infineon (7) 00 JEDEC ID Code of Infineon (8) 00 Module Manufacturer Location xx Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 36 34 54 36 Data Sheet 26 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Table 18 SPD Codes for PC2-4200M and PC2-3200M HYS64T64020KM-3.7-A HYS64T64020HM-3.7-A HYS64T32000KM-3.7-A HYS64T32000HM-3.7-A HYS64T64020LM-3.7-A HYS64T32000LM-3.7-A HYS64T64020KM-5-A HYS64T64020HM-5-A HYS64T32000KM-5-A 32 30 30 30 4B 4D 35 41 20 20 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF HYS64T32000HM-5-A 32 30 30 30 48 4D 35 41 20 20 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF HYS64T64020LM-5-A HYS64T32000LM-5-A x64 1 Rank (x16) Rev 1.1 34 30 32 30 48 4D 35 41 20 20 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF 32 30 30 30 4C 4D 35 41 20 20 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF SPD Codes Product Type Organization 512 MByte x64 2 Ranks (x16) 256 MByte x64 1 Rank (x16) Rev 1.1 34 30 32 30 48 4D 33 2E 37 41 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF 32 30 30 30 4C 4D 33 2E 37 41 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF 32 30 30 30 4B 4D 33 2E 37 41 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF 32 30 30 30 48 4D 33 2E 37 41 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF 512 MB x64 2 Ranks (x16) Rev 1.1 34 30 32 30 4C 4D 35 41 20 20 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF 34 30 32 30 4B 4D 35 41 20 20 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF 256 MB Label Code Jedec SPD Revision Byte# Description 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 127 128255 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) Not used BLANK PC2-4200M-444 PC2-4200M-444 PC2-3200M-333 PC2-3200M-333 Rev 1.1 34 30 32 30 4C 4D 33 2E 37 41 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF 34 30 32 30 4B 4D 33 2E 37 41 20 20 20 20 0x xx xx xx xx xx xx xx 00 FF HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX Data Sheet 27 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Package Outlines 7 Package Outlines 3.8 MAX. 54 0.15 B 1.65 -0.25 0.1 C 2.3 0.2 30 0.15 0.62 0.03 (44.72) D B A 107 214 B 43.38 0.02 106 x 0.4 = 42.4 (3.44) (2.43) 0.4 4.3 1 108 A 2.9 0.1 M C B M 2.6 0.1 A C 0.1 0.8 0.08 Detail of contacts A-A E Contact Area 1.08 -0.04 0.4 0.26 0.02 0.06 C D E 107x GLD09638 B-B 1.3 0.02 0.1 M A B M Burnished, no burr allowed Figure 4 PCB Raw Card A Component Placement L-DIM-214-1 Data Sheet 32 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Package Outlines 2.34 MAX. 54 0.15 B 1.65 -0.25 0.1 C 2.6 0.1 2.3 0.2 0.62 0.03 (44.72) D B A 107 214 B 43.38 0.02 106 x 0.4 = 42.4 30 0.15 A C 0.1 0.8 0.08 0.1 M C B M (3.44) (2.43) 0.4 108 Detail of contacts A-A E Contact Area B-B 1.3 0.02 0.1 M A B M 4.3 1 A 2.9 0.4 0.26 0.02 0.06 C D E 107x GLD09668 Burnished, no burr allowed Figure 5 PCB Raw Card B Component Placement L-DIM-214-2 Data Sheet 33 1.08 -0.04 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X HYS64T[3200/6402]0[H/K/L]M-[3.7/5]-A Double-Data-Rate-Two SDRAM Micro-DIMM Preliminary Product Type Nomenclature (DDR2 DRAMs and DIMMs) 8 Product Type Nomenclature (DDR2 DRAMs and DIMMs) Infineon's nomenclature uses simple coding combined with some propriatory coding. Table 20 provides examples for module and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 21 and for components in Table 22. Table 20 Nomenclature Fields and Examples Field Number 1 Micro-DIMM DDR2 DRAM Table 21 1 2 3 4 HYS HYB 2 64 18 3 T T 4 64 512 5 0 16 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A Example for DDR2 DIMM Nomenclature Values Coding HYS 64 72 T 32 64 128 256 0 .. 9 Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte look up table 1, 2, 4 look up table look up table Field Description INFINEON Modul Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1) 1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding". Table 22 1 2 3 4 DDR2 DRAM Nomenclature Values Coding HYB Constant SSTL1.8 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-533 DDR2-400 Field Description INFINEON Component Prefix DRAM Technology Interface Voltage [V] 18 T Component Density 256 [Mbit] 512 1G 2G 5 6 7 8 9 Raw Card Generation Number of Module 0, 2, 4 Ranks Product Variations 0 .. 9 Package, Lead-Free Status Module Type A .. Z S M R U 5+6 Number of I/Os 40 80 16 7 SO-DIMM Micro-DIMM Registered Unbuffered PC2-4200 4-4-4 PC2-3200 3-3-3 First Second 11 10 9 8 Product Variations Die Revision Package, Lead-Free Status Speed Grade N/A for Components 0 .. 9 A B C F -3.7 -5 10 11 Speed Grade Die Revision -3.7 -5 -A -B Data Sheet 34 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X www.infineon.com Published by Infineon Technologies AG |
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